FIG. 1 schematically illustrates a conventional multiple processor system 10 having a distributed memory system 12 (memories 12a, 12b, and 12c). In the system 10, a separate and dedicated memory is provided to each processor. For example, the memories 12a, 12b, and 12c may be a dynamic random access memory (DRAM) of an appropriate size, for example, 16-Mbit, 8-Mbit, and 4-Mbit DRAMs, respectively. The memories 12a, 12b, and 12c are connected to the corresponding processors 14a, 14b, and 14c via a data bus (32 bit or 16 bit, for example). Each processor accesses its designated memory only, and does not share the memory with other processors.
IC designers can integrate significant densities of memory and logic together on the same chip in order to reduce chip count and system cost (commonly referred to as “System-On-Chip”). When such a multiple processor system is integrated into one integrated circuit (IC) as an embedded system, memories are also embedded using an embedded DRAM process or other high density embedded memory technology. FIG. 2 schematically illustrates a conventional embedded system 20 integrating multiple processors 22 (22a, 22b, and 22c) onto one IC chip along with associated embedded memory blocks 24 (24a, 24b, and 24c). The embedded memory blocks 24 may include DRAM or 1T-SRAM®, available from MoSys Inc. of Sunnyvale, Calif., of selected sizes (logical and physical) for the corresponding processors. However, although the processors and memories are embedded onto one single chip, the memory architecture is substantially the same as that shown in FIG. 1, and the power consumption from the distributed memory system may be still too high for some applications for the embedded system.